Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. In chip packages having two or more dies arranged across a substrate, such as a package substrate or an interposer of the chip package, the dies are generally selected from a common lot according to a predefined performance criteria, which often is speed. Dies having substantially the same speed are further separated into bins having predefined processing characteristics, such as power. Dies are select from the various bins to forming the chip package. The typically assembly technique generally matches dies from bins with the highest and lowest performance for mounting on the substrate. However, such conventional fabrication techniques often do not have a satisfactory product yield, as many dies may not be matched. The unmatched dies undesirably increase fabrication costs.
Therefore, a need exists for improved techniques for fabricating chip packages.